View Single Post
  #25 (permalink)  
Old 04-14-2005, 02:54 AM
Jim Lewis
Posts: n/a
Default Re: VHDL language of choice?

Tim Hubberstey wrote:
> Jim Lewis wrote:
>> If you have a language issue that you think needs to be
>> addressed, you can submit an enhancement request against
>> it at:
>> If you have trouble remembering this, there is a link to
>> it at:

> -- Warning! Rant_Mode <= true
> The problem with this method is that there are some issues that the
> language controllers are simply not willing to address.

I think for future revisions of VHDL all user requests
need to be on the table. To get a good solution, we
need to get many perspectives. One of the challenges
is to translate from a request that suggests an
implementation to the underlying requirement - because
there may be a better way of addressing the requirement
that is already being proposed.

The original language designers have blessed us with a
clean, consistent language. As we move forward, those of
us who decide to answer the call and step into this role,
need to work hard to keep the language clean and consistent.

Don't get discouraged because something was rejected in the
past, however, do keep in mind the rule about standards:

With standards you don't necessarily get what you want,
but you usually will get something you can live with.

Just so you understand the process we are currently are
using (and may become the model for future revisions):
things that are high value and someone is interested
in working on will get worked on. Keep in mind that they
will have to be traded off between other potential candidate
solutions. So far this seems to have been working well.

If you don't have alot of time, working on just one proposal
that has high value to you is great. If you don't feel
up to working on language proposals, even being aware of
what we are doing and telling your vendors which proposals
are of high value to you will ensure that your vendors take
note and start consider how they are going to implement
the features.

Beyond language proposals, if you look at the big differences
between the capability of "C" and VHDL, you will note that it
is not in the langauge capability, but the fact that C has
an extensive number of libraries. VHDL has some ground to
cover with respect to implementing packages.

Again, if you don't feel up to writing these sort of things,
we will need people who try them out. Make sure the use
model is ok. Test them and find bugs.

There is plenty to do. As we finish the fast track phase and
move to the next phase, we are going to need to do more planning.
Once that planning is complete, we will be able to be more
specific about what needs to be done.

Beyond this, while most WG activities are done on a voluntary
basis, LRM editing is a paid position and we need between
$100K and $150K to finish fast track edits. If you know of
an organization who is willing to help us reach our goal,
please let myself or Steve Bailey (VASG Chair) know. Please
note that neither IEEE dues nor IEEE-SA dues nor donations
to IEEE-SA go to fund IEEE standards working groups. Only
donated directly to the working group funding organization
goes to the working group.

Best Regards,
Jim Lewis
VASG Vice Chair
VHDL-200X Fast Track Co-Team lead
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~
Jim Lewis
Director of Training mailto:[email protected]
SynthWorks Design Inc.

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~
Reply With Quote