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Old 04-14-2005, 12:19 AM
Tim Hubberstey
Posts: n/a
Default Re: VHDL language of choice?

Paul wrote:

>> * finally: VHDL code it better human-readable - IMHO ;-)

> I used to think that vhdl would be more readable than verilog, but I've
> seen too much vhdl code that looks like this:
> x := std_logic_vector(to_unsigned((to_integer(unsigned( z1)) +
> to_integer(unsigned(z2))), 9));
> y := std_logic_vector(to_unsigned((to_integer(unsigned( x(7
> DOWNTO 0))) + to_integer(unsigned(x(8
> DOWNTO 8)))), 8));

This really an issue with the standard packages and not the language
itself (a hairline distinction). Many people create their own packages
that crunch this kind of thing down to something reasonable. For
instance, I use a function, AddSLV(vec_1, vec_2, mode), that takes 2
standard_logic_vectors and "adds" them. The "add" function can be signed
or unsigned 2's complement, Gray, etc. as defined by the mode value.

> which I *think* is meant to do the same thing as this nice verilog
> code:
> x = z1 + z2;
> y = x[7:0] + x[8];

You could write the exact equivalent in VHDL by using the unsigned
package instead of the numeric_bit package:

x <= z1 + z2;
y <= x(7 downto 0) + x(8);
^-- not sure about this since I don't use the
unsigned package. Might need to re-size it.

> (Now try to imagine the above vhdl code with really long identifiers
> instead of the short identifiers that I used.)
> Some vhdl proponents believe that readability is synonymous with
> verbosity.

No argument there. I much prefer the [x:y] notation to (x downto y).
It's also a safe bet that something that basic is never going to change.

However, your example isn't really about readability -- it's about
strong (VHDL) vs weak (Verilog) typing. Some people like a
strongly-typed language because of the implicit error checking, others
hate it because the typing "keeps me from doing what I want". It's a
philosophical difference that goes much deeper than just syntax and is
probably just as religious as Mac vs PC or Linux vs Windows.
Tim Hubberstey, P.Eng. . . . . . Hardware/Software Consulting Engineer
Marmot Engineering . . . . . . . VHDL, ASICs, FPGAs, embedded systems
Vancouver, BC, Canada . . . . . . . . . . .
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