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Old 04-14-2005, 12:09 AM
Mike Treseler
Posts: n/a
Default Re: VHDL language of choice?

Tim Hubberstey wrote:

> However, there are some pragmas that *must* be inside the code because
> the tool the pragma is for doesn't have any back-end files. Some code
> coverage and formal verification tools come to mind here.

Thanks for the tip. I will remind myself
not to bother evaluating such tools.
Modelsim seems to do ok on
code coverage without resorting to such hacks.

> -- Synopsys ...
> This caused the synthesis of the block to fail which, since it was a
> block instantiated by many other blocks, caused the entire 18-hour
> synthesis run to fail.

Serious bummer. I'll resolve to keep vendor names
and keywords like "translate" out of my comments.

> My point is that, whether
> you choose to use them or not, pragmas have no business looking like
> comments.

I agree that comments ought to be ignored by all tools.
Some of the vendors use vhdl attributes to do this sort of thing.
At least that eliminates the possible side effects of putting
vendor settings in source code.

-- Mike Treseler
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