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Old 04-13-2005, 11:37 PM
Tim Hubberstey
Posts: n/a
Default Re: VHDL language of choice?

Ralf Hildebrandt wrote:

> Tim Hubberstey wrote:
>> Foremost among these, IMO, is the issue of a built-in pre-processor.
>> Nearly every person I have encountered who is just learning VHDL, but
>> has experience with another language, asks: Why is there no
>> pre-processor/macro capability?
>> From the very beginning (VHDL'87), it has been stated that the
>> designers don't want a pre-processor ...

> Do we need a preprocessor, if something like the generate statements
> would be extended to the signal declaration and to the entity? Such a
> solution would offer configuration using one idea - not two like the
> parameter and defines in Verilog.

Possibly not for pre-processing, as long as the pragma issue is
addressed somehow.

However, I would still like to see a macro capability. Generates are
powerful and can do many things, but sometimes they either just aren't
enough (lack of an "else" clause is a big failing), or are way too complex.
Tim Hubberstey, P.Eng. . . . . . Hardware/Software Consulting Engineer
Marmot Engineering . . . . . . . VHDL, ASICs, FPGAs, embedded systems
Vancouver, BC, Canada . . . . . . . . . . .
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