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Old 04-13-2005, 07:20 PM
Mike Treseler
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Default Re: VHDL language of choice?

Brian Drummond wrote:

> If he had defined x and y as type unsigned, he could have written
> something like
> x := z1 + z2;
> y := x(7 downto 0) + "0000000"&x(8);


> Now there are reasons for reverting to std_logic_vector at the physical
> ports of a chip, but the ":=" form of assignment tells me x and y are
> variables inside a process, so that can't matter here!


Well said.
Thanks for the posting.

Conversion between
std_logic_vector and unsigned
is a simple cast on the
edge assignments.

Most designs have 10 times
more process register bits
than pins on the device.

-- Mike Treseler
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