View Single Post
  #19 (permalink)  
Old 04-13-2005, 04:37 PM
Brian Drummond
Guest
 
Posts: n/a
Default Re: VHDL language of choice?

On 12 Apr 2005 10:47:26 -0700, "Paul" <[email protected]> wrote:

>> * finally: VHDL code it better human-readable - IMHO ;-)

>
>I used to think that vhdl would be more readable than verilog, but I've
>seen too much vhdl code that looks like this:
>
> x := std_logic_vector(to_unsigned((to_integer(unsigned( z1)) +
>to_integer(unsigned(z2))), 9));
> y := std_logic_vector(to_unsigned((to_integer(unsigned( x(7
>DOWNTO 0))) + to_integer(unsigned(x(8
>DOWNTO 8)))), 8));
>
>which I *think* is meant to do the same thing as this nice verilog
>code:



USUALLY that's a warning that you (or the code's writer) hasn't thought
through the design properly.

If he had defined x and y as type unsigned, he could have written
something like

> x = z1 + z2;


x := z1 + z2;
-- clear enough?

> y = x[7:0] + x[8];


// Was the length mismatch deliberate or is it cover for an obscure bug?
// How do unequal-length operands get handled?
// Did it sign extend or zero fill the shorter one?
// If it extends the shorter operand, can I trust it to flag length
// mismatches between the expression and the assignment variable?

y := x(7 downto 0) + "0000000"&x(8);
-- Clear and precise.
-- Yes there are better ways to extend the shorter operand.
-- Doesn't necessarily do the same as the Verilog code because
-- there are a lot of assumptions in the translation...

The VHDL version has the advantage over the Verilog code that the
operand length mismatch was obviously deliberate and handled in a
defined manner, and not an obscure bug waiting to happen.

Now there are reasons for reverting to std_logic_vector at the physical
ports of a chip, but the ":=" form of assignment tells me x and y are
variables inside a process, so that can't matter here!

Of course the above assumes he is using "numeric_std" and not the
non-standard "std_logic_arith" library, whouch would IMO be another
warning of a poorly thought out design.

>Some vhdl proponents believe that readability is synonymous with
>verbosity.


And some don't. But this VHDL proponent believes that the precision is
worth _some_ excessive verbosity, to ensure that the code actually does
what it says it does.

- Brian
Reply With Quote