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Old 04-13-2005, 02:34 PM
Martin Thompson
Posts: n/a
Default Re: VHDL language of choice?

"Paul" <[email protected]> writes:

> > * finally: VHDL code it better human-readable - IMHO ;-)

> I used to think that vhdl would be more readable than verilog, but I've
> seen too much vhdl code that looks like this:
> x := std_logic_vector(to_unsigned((to_integer(unsigned( z1)) +
> to_integer(unsigned(z2))), 9));
> y := std_logic_vector(to_unsigned((to_integer(unsigned( x(7
> DOWNTO 0))) + to_integer(unsigned(x(8
> DOWNTO 8)))), 8));

I would argue that's just bad code - x and y should be unsigned in
this case. It's not very often that you actually want to assign the
result of an arithmetic operation to a boggo vector.

One can write unreadble code in any language - and as someone else has
pointed out, at least the operations in numeric_std are well-defined.


[email protected]
TRW Conekt, Solihull, UK
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