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Old 04-12-2005, 09:02 PM
Kai Harrekilde-Petersen
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Default Re: VHDL language of choice?

Ralf Hildebrandt <[email protected]> writes:

> Paul wrote:
>
>
>>> * finally: VHDL code it better human-readable - IMHO ;-)

>
>> I used to think that vhdl would be more readable than verilog, but I've
>> seen too much vhdl code that looks like this:
>> x := std_logic_vector(to_unsigned((to_integer(unsigned( z1)) +
>> to_integer(unsigned(z2))), 9));

> ...
>> which I *think* is meant to do the same thing as this nice verilog
>> code:
>> x = z1 + z2;


I guess we (at work) are not the only ones that have made a package
with a bunch of typecasting functions to reduce this problem as much
as possible. With our 'type_conv' package the above would look like:

x := to_slv(to_uns(z1) + to_uns(z2), 9);

Which is a reasonable compromise. But I concur with the general
comment about VHDL's verbosity

> And finally: It is my personal opinion, that it is better
> readable. ;-)


IMHO, it ain't.

> It started learing VHDL with only little knowledge about the C
> syntax. Now, as I have learned C, Verilog is much more readable, but
> still my opinion is the same. When I do Verilog I code it like VHDL
> and it looks much better than in examples. But again: IMHO!


I learned C first, then Verilog, and then VHDL.

I've learned to loathe all of them for their individual shortcomings.

I think it was Dave Bishop who said, when asked about the difference
between Verilog and VHDL:

Verilog was designed by a bunch of hardware guys who didn't know a
thing about designing software. We had to beat on it to make it work.

VHDL was designed by a bunch of software guys who didn't know a thing
about designing hardware. We had to beat on it to make it work.


Kai
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Kai Harrekilde-Petersen <khp(at)harrekilde(dot)dk>
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