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Old 04-12-2005, 08:12 PM
Ralf Hildebrandt
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Default Re: VHDL language of choice?

Paul wrote:


>> * finally: VHDL code it better human-readable - IMHO ;-)


> I used to think that vhdl would be more readable than verilog, but I've
> seen too much vhdl code that looks like this:
>
> x := std_logic_vector(to_unsigned((to_integer(unsigned( z1)) +
> to_integer(unsigned(z2))), 9));

....
> which I *think* is meant to do the same thing as this nice verilog
> code:
>
> x = z1 + z2;


Yes - I agree, this is the point, where VHDL is not well readable, but
remember two things:
* It is well-defined if signed or unsigned arithmetics are used (as long
as you use IEEE.Numeric_std.ALL). For addition you don't care about
this, but for a comparison it is important.
* How many of these constructs do you have in a typical design? O.k. -
quite a lot if you do DSP arithmetics, but normally these things are
rare. (I often try to re-use adders as they have a speed impact and
are area-expensive. Therefore 5 such things in the whole design is a
big number.)



And finally: It is my personal opinion, that it is better readable. ;-)
It started learing VHDL with only little knowledge about the C syntax.
Now, as I have learned C, Verilog is much more readable, but still my
opinion is the same. When I do Verilog I code it like VHDL and it looks
much better than in examples. But again: IMHO!

Ralf
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