View Single Post
  #15 (permalink)  
Old 04-12-2005, 06:47 PM
Paul
Guest
 
Posts: n/a
Default Re: VHDL language of choice?

> * finally: VHDL code it better human-readable - IMHO ;-)

I used to think that vhdl would be more readable than verilog, but I've
seen too much vhdl code that looks like this:

x := std_logic_vector(to_unsigned((to_integer(unsigned( z1)) +
to_integer(unsigned(z2))), 9));
y := std_logic_vector(to_unsigned((to_integer(unsigned( x(7
DOWNTO 0))) + to_integer(unsigned(x(8
DOWNTO 8)))), 8));

which I *think* is meant to do the same thing as this nice verilog
code:

x = z1 + z2;
y = x[7:0] + x[8];

(Now try to imagine the above vhdl code with really long identifiers
instead of
the short identifiers that I used.)

Some vhdl proponents believe that readability is synonymous with
verbosity.

Paul

Reply With Quote