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Old 04-12-2005, 04:09 PM
Ralf Hildebrandt
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Default Re: VHDL language of choice?

Tim Hubberstey wrote:


> Foremost among these, IMO, is the issue of a built-in pre-processor.
> Nearly every person I have encountered who is just learning VHDL, but
> has experience with another language, asks: Why is there no
> pre-processor/macro capability?
>
> From the very beginning (VHDL'87), it has been stated that the
> designers don't want a pre-processor ...


Do we need a preprocessor, if something like the generate statements
would be extended to the signal declaration and to the entity? Such a
solution would offer configuration using one idea - not two like the
parameter and defines in Verilog.


Ralf
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