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Old 04-12-2005, 02:15 PM
Brian Drummond
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Default Re: VHDL language of choice?

On Mon, 11 Apr 2005 16:50:17 -0700, Mike Treseler
<[email protected]> wrote:

>Tim Hubberstey wrote:
>
>> Foremost among these, IMO, is the issue of a built-in pre-processor.
>> Nearly every person I have encountered who is just learning VHDL, but
>> has experience with another language, asks: Why is there no
>> pre-processor/macro capability?

>
>Hi Tim,
>
>I came from a hardware background and found
>it odd when first maintaining a C program that I had to
>wade through a nest of #ifndefs and hack
>some #defines to get the options right.
>Maintaining the *almost* C-like macros
>can also be challenging for a bit bouncer.


I came to C from a more formal software background (ALGOL-W, then
Modula-2 and a very clean OO language), and found much the same thing,
plus the non-referentially-transparent nature of C style pre-processing
makes it virtually unusable except for trivial hacks.

Even then it leads to pretty unstable systems. Part of the problem is
that it's untestable, or at least untested by any compiler system I
know; only the processed code undergoes syntax checking (does anyone
know of a pre-compiler that traverses every branch and reports on errors
in the currently unreachable ones?), and that has several interesting
ways of generating (or at the very least) obscuring errors.

Some of its common uses are to overcome problems in C that shouldn't be
there in the first place, and VHDL doesn't have anyway. Such as the lack
of a proper import mechanism (package/library/use in VHDL;
FROM ... IMPORT in Modula-2).

I for one would be very unhappy about adding ways of introducing so many
bugs into VHDL, and the only way to avoid it would be a much more
rigorous and heavyweight approach than the C pre-processor.

- Brian
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