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Old 04-07-2005, 07:36 AM
Phil Tomson
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Default Re: VHDL language of choice?

In article <[email protected]>,
Jim Lewis <[email protected]> wrote:
>
>There is an on-going revision of VHDL in progress. It is
>adding a number of significant features (such as uncostrained
>arrays of arrays - very useful in parameterized models),
>generics on packages, packages for fixed and floating
>point, integration of PSL, and language simplification
>(case and if statements). In the area of math, VHDL will
>have an advantage over Verilog/System Verilog as they don't
>have their own solution for these fixed and floating point.
>For more details see the papers page at:
>http://www.synthworks.com/papers
>
>In the next revision (immediately following this one) we will
>be adding enhanced verification features, similar to what
>System Verilog has done (such as constrained random). We will
>also be using the new features of the language (specifically
>generics on packages) to write packages that implement advanced
>verification data structures (such as queues, FIFOS, and
>memories).
>


Any changes planned for the scope of user defined attributes? As in will
they be accessable outside of the package they're defined in? (not being
able to do this now tends to make them not very useful). Allowing user
defined attributes on types to be accessable outside of the package
they're defined in, for example, would seem to move VHDL in a more OO
direction (which should be a good thing

As far as VHDL vs. Verilog popularity goes: comp.lang.vhdl seems to get
consistently more traffic then comp.lang.verilog.

Phil
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