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Old 04-04-2005, 07:22 PM
Ralf Hildebrandt
Posts: n/a
Default Re: VHDL language of choice?

Herb T wrote:

> I was talking to some electronics buffs on a chat channel, and they
> were telling me that only Universities and DOD uses VHDL. I thought it
> was hogwash, but wanted to find out if many commercial companies are
> using the language earnestly. The resident HDL expert was saying
> verilog is the language of choice these days. Is that true? I
> personally prefer VHDL because the I already have too many reference
> materials on how to use it.

Most of the american companies use Verilog while in Europe VHDL is common.

I prefer VHDL, too, because
* it is strongly typed and typing errors, that did not lead to syntax
errors are detected more often
* it avoids all these ugly cases mentioned in "verilog coding styles,
that kill" (Clifford Cummings )
* it protects better from writing to one signal from different processes
* signed / unsigned arithmetics are defined more preceisely (with the
disadvantage of having all these type conversions)
* handling of multi-dimensional vectors is possible and handling of
two-dimensional vectors is much easier
* generic parameters and generate statements are easier to use than
Verilog parameters and defines
* finally: VHDL code it better human-readable - IMHO ;-)

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