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Old 04-04-2005, 09:20 AM
Jonathan Bromley
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Default Re: VHDL language of choice?

On 4 Apr 2005 00:14:45 -0700, "Neo" <[email protected]> wrote:

>verilog is widely prevalent in asic design world and is the language of
>choice. But in FPGA design community both are widely used.

It isn't that simple; there are many serious commercial ASIC/custom
outfits that use VHDL.

Sadly, though, it is true that VHDL simply doesn't seem to have the
momentum that Verilog has. I know that Jim Lewis and all the
great people involved in VHDL-200x are working hard to rectify
that, but in the last analysis the only sensible approach for
an individual engineer is: become bilingual in VHDL and Verilog.
Jonathan Bromley, Consultant

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