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Old 11-29-2004, 06:34 AM
systolic
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Default Questions about Timing analysis and Component Instantiation.

I am using Quartus for my VHDL coding. I have 2 questins here. Could
someone please help me on them. TIA.

1. For Quartus, there are lots of built-in LPM and ALT mega funcitons. I
want to implement 2 RAMs in one module. Both of them use the same ALT
mega function with different bus lengthes. I am supposed to just declare
the component once. But how could instantiate it twice for 2 RAMs with
different bus lengthes? Or I should encapsulate these 2 RAMs seperately
into 2 different user-customised componentsbased based on the same ALT
mega function, then instantiat my components.

2. When I was doing the timing simulation with Quartus, the finaltiming
analysis gives the report that the module can have the maximum clock
around 56MHz. The clock I had for timing simulation is only 5MHz. But if
I change the clock from 5MHz to 10MHz, thetiming simulation result will
not be correct any more. What caused that? is that because the timing
simulation is software-based simulation, it needs more time to compute
all kinds of outputs, inputs of logic elements for the whole module?

Thanks for any advices or comments. Maybe I am asking wrong questions.

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