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Old 11-01-2003, 09:02 PM
David Bishop
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Default Re: Compare pairs of bits between two slv's ?


This is why we are thinking of putting vector reduction into
VHDL.

Try this:

set := or_reduce (mask and trig);

You will find a copy of "or_reduce" at:
http://www.vhdl.org/vhdlsynth/

This is functionality we also plan to add in 1164 as well.

Tony Benham wrote:

> I've been puzzling how I can write concise vhdl that will basically set a
> bit if any pair of bits in two slv's are both hi ?
> A sort of pseudo code for what I want to do is as follows
> mask : std_logic_vector(7 downto 0) ;
> trig : std_logic_vector(7 downto 0) ;
> set : std_logic;
>
> set <= '0' ;
> for i in 0 to 7
> If mask(i) AND trig(i) = '1'
> set <= '1' ;
> end if ;
> end for ;
>
> In english, if any pair of bits in the two slv's are both hi, the set will
> be set to one, else zero
>
> I thought about using For-Generate, but I'm puzzled how to apply for this
> case ?
>
> Regards
> Tony
>
>


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