Compare pairs of bits between two slv's ?
I've been puzzling how I can write concise vhdl that will basically set a
bit if any pair of bits in two slv's are both hi ?
A sort of pseudo code for what I want to do is as follows
mask : std_logic_vector(7 downto 0) ;
trig : std_logic_vector(7 downto 0) ;
set : std_logic;
set <= '0' ;
for i in 0 to 7
If mask(i) AND trig(i) = '1'
set <= '1' ;
end if ;
end for ;
In english, if any pair of bits in the two slv's are both hi, the set will
be set to one, else zero
I thought about using ForGenerate, but I'm puzzled how to apply for this
case ?
Regards
Tony
