View Single Post
  #1 (permalink)  
Old 10-08-2003, 09:50 AM
Ingmar Seifert
Guest
 
Posts: n/a
Default Modelsim 5.7c behaviour

Hallo,

I use Modelsim 5.7c since yesterday. Before this I uses 5.6e.
I now get a warning when compiling a vhdl-file, in the following form:

WARNING[10]: E:/Hu-Moment-Berechnung/src/hu_unit.vhd(162): Synthesis
Warning: Signal "state" appears in process "steuerung"'s senstivity
list, but it is not used in the clock expression or reset expression.

I have set all signals, thta are read in a process in it's sensitivity
list. Former versions of modelsim showed an error, when the signal names
were missing. This version schows an error, when the signals are there.

What's wrong with my code or modelsim?


My code:
steuerung: PROCESS(HU_UNIT_EN, div_xs_quotient, div_xs_rdy, state,CLK,RESET)
BEGIN
IF RESET = '1' THEN
state <= IDLE;
div_xs_en <= '0';
xs_s <= (others=>'0');
ELSIF CLK'EVENT AND CLK='1' THEN
CASE state IS
-- IDLE = Startzustand nach RESET
WHEN IDLE =>
IF HU_UNIT_EN = '1' THEN
state <= XS;
END IF;
div_xs_en <= '0';

Thanks for your help in advance.
Regards,
Ingmar Seifert

Reply With Quote