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Old 10-03-2003, 05:14 AM
Allan Herriman
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Default Re: how to test benching a bidircetional port?

On Thu, 2 Oct 2003 15:56:10 +0200, "jtj"
<[email protected]> wrote:

>Hi All
>
>I would like to test a bi-directional port in a test bench.
>To generate the test bench I use Bencher, a GUI tool that is bundled with
>Xilinx ISE.
>Assigning OUTDATA to PADPIN works fine but when I try to assign a value to
>PADPIN form the test bench
>Modelsim gives the following error: "Nonresolved signal padpin has multiple
>sources."
>
>What is the trick? -Any help is appreciated since I'm starting to be
>frustrated.


Change that signal from std_ulogic(_vector) to std_logic(_vector).
This will make it a resolved signal, which matches what you are trying
to do.
BTW, The 'u' in std_ulogic stands for 'unresolved'.

Allan.
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