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Old 10-02-2003, 03:56 PM
Posts: n/a
Default how to test benching a bidircetional port?

Hi All

I would like to test a bi-directional port in a test bench.
To generate the test bench I use Bencher, a GUI tool that is bundled with
Xilinx ISE.
Assigning OUTDATA to PADPIN works fine but when I try to assign a value to
PADPIN form the test bench
Modelsim gives the following error: "Nonresolved signal padpin has multiple

What is the trick? -Any help is appreciated since I'm starting to be

Thanks in advance


library IEEE;
use IEEE.std_logic_1164.all;

entity BIPAD is port (
PADPIN : inout std_ulogic_vector(15 downto 0);
RD : in std_ulogic;
WR : in std_ulogic;
OUTDATA : in std_ulogic_vector(15 downto 0);
INDATA : out std_ulogic_vector(15 downto 0));
end BIPAD;

architecture test of BIPAD is

PADPIN <= OUTDATA when (WR = '1' and RD = '0') else "ZZZZZZZZZZZZZZZZ";
-- PADPIN <= OUTDATA when (WR = '1' and RD = '0'); --else
INDATA <= PADPIN when (WR = '0' and RD = '1');
end test;

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