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Old 10-02-2003, 04:54 AM
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Default what do you guys do if Synopsys DC says it runs out of memory?

Dear all,

This might be more towards synthesis...

I keep getting "run out of memory" error message from my Synopsys Design
Compiler... The strangest thing is that the same design, sometimes can pass,
sometimes will fail "running out of memory"... Sometimes the "memory value"
is 4GB, sometimes it is 1GB...

Here is my script file and here is my error message... What do you guys do
when you meet with such problem? Could you share with some of your

Thanks a lot



$SYNOPSYS/sparcOS5/syn/bin/dc_shell-t <<!
redirect myidct_zero1cmu.log {
analyze -format vhdl -lib WORK {myidct_zero1cmu.vhd}
elaborate myidct_zero1cmu -arch "flex" -lib WORK -update
ungroup -all -flatten
create_clock "CLK" -name "CLK" -period 60
compile -map_effort medium -area_effort high
current_design .
report_timing -path full -delay max -max_paths 1 -nworst 1 >
report_area >> reports/\$current_design.rep
report_resources -hierarchy >> reports/\$current_design.rep
write -format vhdl -hierarchy -output "mapped/\$current_design.vhd"
write -format verilog -hierarchy -output "mapped/\$current_design.v"
echo "\nScript Done\n"
echo "\nChecking Design\n"


Error message:

90 > ./scripts/myidct_zero1cmu.scr

Behavioral Compiler (TM)
DC Professional (TM)
DC Expert (TM)
DC Ultra (TM)
VHDL Compiler (TM)
HDL Compiler (TM)
Library Compiler (TM)
Power Compiler (TM)
DFT Compiler (TM)
BSD Compiler
DesignWare Developer (TM)
DesignPower (TM)

Version 2001.08-SP2 for sparcOS5 -- Feb 05, 2002
Copyright (c) 1988-2001 by Synopsys, Inc.

This program is proprietary and confidential information of Synopsys, Inc.
and may be used and disclosed only as authorized in a license agreement
controlling such use and disclosure.


Out of memory.
(Memory allocated = 4103759 K bytes)

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