Hi all,

Is there any operator to divide a std_logic_vector, either by another
std_logic_vector or by an integer?

I am using the following code at the moment

temp := CONV_INTEGER(buf2) / q ;
ZRLOut <= CONV_STD_LOGIC_VECTOR(temp,11);

where buf2 and ZRLOut are signals of type std_logic_vector, temp is a
variable of type integer, and q is a signal of type integer.

Thanks
Ciarán Hughes

This works fine in behavioural simulation, but when I run a post
translate simulation, the division seems to be ignored, i.e. ZRLOut is
equal buf2. It is like the division can't be synthesised, and is
ignored (like the after statement).

Thanks,
Ciarán Hughes