Thread: Event
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Old 09-17-2003, 08:02 AM
Michael
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Default Event

hello
I'm trying to assign a value to a signal, LAST, when there's an event
on DEV_DATA and count <= 0, the following is the code:
out_logic: process(current_state, DEV_DATA, DEV_ADDR, DEV_RTYP,
DEV_RDY, DEV_GRNT,
FRAME, C_BE, IRDY, TRDY, DEVSEL, AD)
begin
case current_state is
when "00010" =>
IRDY <= '1';
if DEV_DATA'event and count <= 1 then
LAST <= '1';
else
LAST <= '0';
...

I'm getting a synthesis error saying "unsupported Clock statement".
DEV_DATA is declared as a port, inout std_logic_vector(7 downto 0) and
count is signal count : std_logic_vector(2 downto 0).

please help

thank you
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