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Old 06-26-2003, 06:20 PM
Mike Treseler
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Default Re: event in state machine

Troels Smit wrote:

> What is the "synchronous template" ??

see:
http://groups.google.com/groups?q=vh...late+spaghetti

> What I need is to interface the DAC AK4520A. It has three control
> signals "MCLK", "SCLK" and "LRCK".
>
> These signals are connected to my clk as follows (counter is
> incremented on each clk cyclk)
>
> sclk <= counter(2);
> mclk <= counter(0);
> lr <= counter(8);
>
> Now, on an LR'event I would like to send a serial word on the next 20
> sclk'cycles, and then wait for the next lr'event.
>
> How would you write that in VHDL ?

--------------------------------

I would write a process using the synchronous template.
Lets say your fpga clock is 40MHz and your generated
mclk is 10MHz. Now the process can generate clocks
or controls for the other inputs with a 50nS resolution.

A shift register with enable can drive the serial data.

To generate synchronous events, consider
using a procedure call like ck_rising(lr, last_lr, lr_rising);
by first declaring the functions below.

-- Mike Treseler

-------------------------

function now_high (std_arg : std_ulogic) -- input bit
return boolean is begin
if std_arg = '1' then return true;
else return false;
end if;
end function now_high;

procedure ck_rising(watch : in std_ulogic;
last_low : inout boolean;
result : out boolean)
is begin
result := now_high(watch) and last_low;
-- check for active edge based on

-- variable from last time;
last_low := now_low(watch);
-- assign variable for next time



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