View Single Post
  #6 (permalink)  
Old 06-26-2003, 08:59 AM
Troels Smit
Guest
 
Posts: n/a
Default Re: event in state machine

What is the "synchronous template" ??

I would like to make sure that Im doing this the easiest way:

What I need is to interface the DAC AK4520A. It has three control
signals "MCLK", "SCLK" and "LRCK".

These signals are connected to my clk as follows (counter is
incremented on each clk cyclk)

sclk <= counter(2);
mclk <= counter(0);
lr <= counter(8);

Now, on an LR'event I would like to send a serial word on the next 20
sclk'cycles, and then wait for the next lr'event.

How would you write that in VHDL ?
(You have a parallel serial converter with enable at your disposal,
giving data with sclk speed)

Best Regards,
Troels Smit

Mike Treseler <[email protected]> wrote in message news:<[email protected]>...
> Troels Smit wrote:
>
> >
> > When in a state, why is it not ok to listen for an event of another signal ??

>
> For simulation, that would work. It's legal VHDL.
>
> For synthesis you should use the synchronous template.
> The only event in synthesis is the rising edge of the clock.
> Other "events" become synchronous strobes
> Clock inputs to the dflops are not used for
> any signal other than clk.
>
> _|___|___|__ clk'event
> _________________
> ______________/ my_output
> ___
> _______________/ \__ my_event
>
> -- Mike Treseler

Reply With Quote