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Old 06-25-2003, 07:04 PM
Mike Treseler
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Default Re: event in state machine

Troels Smit wrote:

> When in a state, why is it not ok to listen for an event of another signal ??

For simulation, that would work. It's legal VHDL.

For synthesis you should use the synchronous template.
The only event in synthesis is the rising edge of the clock.
Other "events" become synchronous strobes
Clock inputs to the dflops are not used for
any signal other than clk.

_|___|___|__ clk'event
______________/ my_output
_______________/ \__ my_event

-- Mike Treseler

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