On Nov 28, 3:16 pm, John_H <[email protected]> wrote:
> [email protected] wrote:

> Are you designing a board with a production run of three that you'll be
> assembling with the toaster-oven technique?
>
> If you're using a professional assembly house, there is post-assembly
> testing that will test for shorts. If you have a production run too
> small for a bed-of-nails tester, there are still flying-lead
> manufacturing defect analyzers that can check your board for shorts.
>
> Why design in "protection" that limits your signal characteristics when
> all you're protecting from is manufacturing faults? If you were cycling
> connecting the FPGA in and out of a connector over and over to varying
> equipment, I could understand some concern. But for soldered-on chips?

It's for a test setup, where I will test different fpga <-> device
setups. No production run at all, not even a prototype one.
I have bought a 100 ohm series resistor net package. Which will limit
any shorts to 33mA. And I think the rise times will be ok with this. t
= RC = 100*10pF (worst case Sp3E) = 1ns. The sp3e datasheet says max
100mA, I hope this will protect the fpga for those minutes it takes to
test the setup.