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Old 11-28-2007, 12:59 AM
L. Schreiber
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Default area group constraint problem

Hello together,

in my vhdl design for ISE 9.2 I want to partition the component
instances of the submodules in my toplevel into defined areas of my fpga ic.

I have never done this but had seen some examples before, where it might
have worked (e.g. projects with reconfiguration).

So I adapted my ucf-file accordingly by adding several area group
constraints and assigned an instance for each area group like in this
short example snippet:

AREA_GROUP "ag1" RANGE = SLICE_X0Y0:SLICE_X50Y50;
INST instance_name_of_first_component_from_toplevel AREA_GROUP = ag1;
AREA_GROUP "ag2" RANGE = SLICE_X51Y0:SLICE_X100Y50;
INST instance_name_of_second_component_from_toplevel AREA_GROUP = ag2;
....

But now I'm getting an error (while implementation stage - don't know
exactly at the moment). The error message says roughly, that the
instances cannot be found (something like that) and i'm proposed to
delete the relevant constraint to go on.

I use the label name of the component port map statement in my toplevel
as the instance names inside the ucf.

Is this wrong or what's the problem? Any suggestions?

I can't post the exact error message at the moment, but it will be given
later if it's necessary.


I have read, that it is possible to generate or extract such area
constraints by using the floorplanner. Does anyone know a helpful and
not too sparse tutorial for the floorplanner, especially for my purpose?


Thanks a lot.
L. Schreiber
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