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Old 11-26-2007, 06:47 PM
Mike Treseler
Posts: n/a
Default Re: vhdl state machine

[email protected] wrote:

> I just want to find out if I have to provide a constraint on enable so
> that the synthesis tool understands that the enable1 doesnt become
> high every clock cycle and that the state machine wont miss any
> enable='1' input coming in and the desing would funtion properly ? or
> is it that synthesis and post sysnthesis tools dont care about this at
> all?

Synthesis is pretty clever with this
and I wouldn't expect that any constraint
other than Fmax is needed. If I can't make
Fmax, I much prefer pipelining or ready/ack
strobes to oddball timing constraints.

-- Mike Treseler
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