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Old 11-24-2007, 08:00 AM
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Default vhdl state machine

I have a following state machine. enable is an input comiing from a
accumulate core. Now the total number of inputs to be accumulated
varies but is always greater than 5.so the maximum frequency of
enable becoming high is every 5th cycle or more.
I just want to find out if I have to provide a constraint on enable so
that the synthesis tool understands that the enable1 doesnt become
high every clock cycle and that the state machine wont miss any
enable='1' input coming in and the desing would funtion properly ? or
is it that synthesis and post sysnthesis tools dont care about this at
all?


process(clock,reset)
begin
if reset = '1' then
state1 <= IDLE;
.....................
....................................
elsif clock'event and clock = '1' then

case state1 is
when IDLE1 =>
if enable= '1' then
state1 <= M1 ;
else
state1 <= IDLE1;
end if;


when M1 =>
TD <= numout;
state1 <= M3;
when M3 =>
................
..................................
state1 <= M4;
...................
.................................

when M4 =>..
....................................
state <= IDLE1;


end case;
end if;
end process;


regards
ng
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