Re: Quartus II warning: "pass-through logic has been added"
What has happend to c.a.f? Only rickman was even close to being on the
ball.
Altera agree that I've found a bug and sent me a temporary workaround
(I haven't yet tested it):
module single_port_ram
(
input [(DATA_WIDTH-1):0] data,
input [(ADDR_WIDTH-1):0] addr,
input we, clk,
output [(DATA_WIDTH-1):0] q
);
parameter DATA_WIDTH = 8;
parameter ADDR_WIDTH = 6;
// Declare the RAM variable
reg [DATA_WIDTH-1:0] ram[2**ADDR_WIDTH-1:0];
reg [ADDR_WIDTH-1:0] addr_reg;
always @ (posedge clk)
begin
// Write
if (we) ram[addr] <= data;
addr_reg <= addr;
end
// Read returns NEW data at addr if we == 1'b1. This is the
// natural behavior of TriMatrix memory blocks in Single Port
// mode
assign q = ram[addr_reg];
endmodule
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