View Single Post
  #2 (permalink)  
Old 11-18-2007, 07:53 PM
Posts: n/a
Default Re: synthesizing vqm with parameters with quartus 7.1sp1

<[email protected]> wrote in message
news:[email protected]m...
> Hi,
> I have a verilog module in my project, which is instantiated in the
> design 3 times, each time with different parameters. I generated 3
> different vqm files outside the Quartus project (with Synplify), one
> for each instantiation. How can I tell Quartus which vqm file should
> be linked to its appropriate block?

By writing the code that instantiates the blocks


Reply With Quote