View Single Post
  #7 (permalink)  
Old 11-15-2007, 09:30 PM
Duane Clark
Posts: n/a
Default Re: synopsys translate_off

Pasacco wrote:
> Thank you for reply.
> When I simulate, I do not see any signal toggling in the waveform,
> because BRAMs are unconnected.
> Actually the "pcores" are provided by a vendor.
> I could modify the VHDL code, but it is too time consuming.
> According to your reply, there might exist "specific Virtex2" library
> for the BRAMs.
> Name of the BRAM primitive is "ram_dp".

I am a little puzzled by that statement. Earlier you said:

> When I try "vcom -work work testbench.vhd", then following warning
> occurs.
> -----------------------
> Warning: Component instance "ramx32 : ramb16_s36_s36" is not bound.
> -----------------------

In that case, the BRAM primitive name is ramb16_s36_s36. That primitive
is a standard one available in the Xilinx unisim library.

> Are there any way to find the Virtex2 library, to simulate with
> Modelsim?
> Maybe my problem is not a "library problem".

Yes, it is a library problem. Your vendor appears to be doing things in
a weird way, and a bit more info is needed to figure out what they are

Show all the library declarations in the file (not just the virtex2 ones).

If there is a component declaration for the bram at the beginning of the
architecture (that is, before the 'begin' statement), show that.

Show the component instantiation of the bram within the body of the
architecture. If there are multiple instantiations, just show one.
Reply With Quote