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Old 11-15-2007, 04:08 AM
Andrew FPGA
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Default Xilinx Chipscope Pro in EDK system - ILA:how specify separate signalsfor data capture and triggering?

Hi,
This is an embarrassing question to be asking - how does one attach
signals from the edk design to the chipscope ILA? When I sit down at
my desk to debug with a benchtop logic analyser, the first thing I do
is attach the probes to the pcb - I kinda expected it would be simple
and straightforward with chipscope pro also?

I'm using EDK 9.1i, sp3. I used the debug->debug config menu and
selected an ILA. Its easy to select signals and add them to Trig0. But
if I want the trigger and data capture signals to be different, where
and how do I attach signals in my design to the data capture port on
the ILA?

(I have limited resources remaining on my FPGA and I only need a few
simple signals connected to the trigger input, but I want a wider
selection of signals captured in the trace buffer)

I tried manually editing the ILA component in the .mhs file, by adding
the entry below:

PORT DATA =
EthInterfaceTimestamp_0_rx_dv_falling_edge_r_to_ch ipscope_ila_0 &
EthInterfaceTimestamp_0_rx_dv_rising_edge_r_to_chi pscope_ila_0 &
EthInterfaceTimestamp_0_tx_en_falling_edge_r_to_ch ipscope_ila_0 &
EthInterfaceTimestamp_0_tx_en_rising_edge_r_to_chi pscope_ila_0 &
EthInterfaceTimestamp_0_timestamp_to_chipscope_ila _0

Which caused edk to crash...Is editing the .mhs file ok?

Regards
Andrew


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