View Single Post
  #5 (permalink)  
Old 11-12-2007, 05:13 PM
HT-Lab
Guest
 
Posts: n/a
Default Re: Strange VHDL Error


"Sascha Frank" <[email protected]> wrote in message
news:[email protected]
>
>> Maybe just use "end package;" instead of "end package RISC_Pkg;"?

>
> Thanks for your answer Dave. The problem is, that I am using Modelsim 5.7
> and that I have a tool that is compatible with Modelsim 6.1.
>
> In other words, I have to do a lot of work by hand so that it works
> with the older Modelsim version.
>
> The tool outputs
>
> component TEST is
>
> whereas the older Modelsim just accepts
>
> component TEST
>
> so there are some issiues. Anyone an idea for a workaround?
> Or do I have to right a PERL script that parses me the VHDL file
> and corrects it accordingly?


You are using VHDL93 syntax with VHDL87, try vcom -93 xx.vhd

Hans
www.ht-lab.com




>
> Many thanks!
>



Reply With Quote