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Old 11-12-2007, 04:47 PM
Sascha Frank
Posts: n/a
Default Re: Strange VHDL Error

> Maybe just use "end package;" instead of "end package RISC_Pkg;"?

Thanks for your answer Dave. The problem is, that I am using Modelsim
5.7 and that I have a tool that is compatible with Modelsim 6.1.

In other words, I have to do a lot of work by hand so that it works
with the older Modelsim version.

The tool outputs

component TEST is

whereas the older Modelsim just accepts

component TEST

so there are some issiues. Anyone an idea for a workaround?
Or do I have to right a PERL script that parses me the VHDL file
and corrects it accordingly?

Many thanks!

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