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Old 11-12-2007, 04:20 PM
Sascha Frank
Posts: n/a
Default Re: Strange VHDL Error

Sascha Frank wrote:

> When I am running it with Modelsim I get the following error:
> Package_LTRISC32ca_gen.vhd(355): near "package": expecting: ';'

Just found the error, I just have to leave out the package in the end
then it works.

end RISC_Pkg;

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