View Single Post
  #1 (permalink)  
Old 11-12-2007, 03:55 PM
Sascha Frank
Guest
 
Posts: n/a
Default Strange VHDL Error

Hi

I have a simple package that looks as follows:

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;


package RISC_Pkg is

-- Clock type
subtype T_clk is std_logic;

-- Reset type
subtype T_rst is std_logic;

subtype T_PIPE_REG_CTRL is std_logic;

subtype T_PREG_FE_DC_dest_pi is unsigned(7 downto 0);
subtype T_FLAG_PREG_FE_DC_dest_pi is std_logic;
subtype T_DATABUS_FE_DC_dest_pi is unsigned(7 downto 0);
subtype T_FLAGBUS_FE_DC_dest_pi is std_logic;

.....

subtype T_DATABUS_data_mem is unsigned(31 downto 0);
subtype T_FLAGBUS_data_mem is std_logic;

end package RISC_Pkg;

When I am running it with Modelsim I get the following error:

Package_LTRISC32ca_gen.vhd(355): near "package": expecting: ';'

But there is clearly a semicolon at "end package LTRISC32ca_PKG". I
havent forgotten any semicolons in between? Anyone an idea what the
issue could be?

Many thanks!

Reply With Quote