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Old 11-10-2007, 06:53 PM
John_H
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Default Re: FIFO interface design

Readon wrote:
> On Nov 9, 10:54 am, Gabor <[email protected]> wrote:
>> On Nov 8, 8:25 pm, Readon <[email protected]> wrote:
>>> On Nov 9, 8:07 am, Dave Pollum <[email protected]> wrote:
>>>> On Nov 8, 8:15 am, Readon <[email protected]> wrote:


>>>>> i want to read & write data to/from a fifo placed in fpga. MCU's
>>>>> external bus is connected to the chip. I am using the sync-fifo ip of
>>>>> Altera CycloneII. The data bus and control signal are connected to
>>>>> fifo directly. it's unfortune that when i read once from bus, data
>>>>> would be read twice from fifo because there are two clock rising edges
>>>>> during read signal(low active) is resetted. I think it will read more
>>>>> datas from fifo if the read signal is resetted long enough.
>>>>> Is there any good design for fifo interface connecting on the
>>>>> exteranl bus?


>>>> Using a Synchronous FIFO implies that the read clock and the write
>>>> clock are in the same clock domain. Is your MCU supplying the FIFO's
>>>> clock or is the FPGA supplying the MCU's clock? If the clock sources
>>>> are different, then you either need an Asynchronous FIFO, or you need
>>>> to run the MCU and FPGA from the same clock.
>>>> HTH
>>>> -Dave Pollum


>>> It is in different clock, i tried altera's asynchronous FIFO which
>>> need two extra clock for reading.
>>> is there any better solution?


>> If your MCU is running much slower than the FPGA, you can use the
>> FPGA's internal clock to run the synchronous FIFO, and a little
>> state logic to generate the necessary (single cycle) pulses for
>> read and write from the MCU interface signals.


> unfortunately, the problem i met is on the contrary. MCU is much
> faster then FPGA, about 4 times.


I can get 600 Mb/s connections on a $5 FPGA. I don't know any fast MCUs
though the front side bus on some embedded processors can get pretty fast.

It sounds like you have an extremely simple logic problem. The read
from the MCU is too wide compared to the sync FIFO's clock.

Change that! If you know that you'll only have one read during a read
signal from the MCU, use that information to only assert the read
control to the sync FIFO once. *Do not* connect the double-wide read
pulse directly to the MCU. This is very, very simple logic.
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