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Old 11-10-2007, 06:04 PM
John Retta
Posts: n/a
Default Re: FIFO interface design

Readon wrote:
> On Nov 9, 10:54 am, Gabor <[email protected]> wrote:
>> On Nov 8, 8:25 pm, Readon <[email protected]> wrote:
>>> On Nov 9, 8:07 am, Dave Pollum <[email protected]> wrote:
>>>> On Nov 8, 8:15 am, Readon <[email protected]> wrote:
>>>>> i want to read & write data to/from a fifo placed in fpga. MCU's
>>>>> external bus is connected to the chip. I am using the sync-fifo ip of
>>>>> Altera CycloneII. The data bus and control signal are connected to
>>>>> fifo directly. it's unfortune that when i read once from bus, data
>>>>> would be read twice from fifo because there are two clock rising edges
>>>>> during read signal(low active) is resetted. I think it will read more
>>>>> datas from fifo if the read signal is resetted long enough.
>>>>> Is there any good design for fifo interface connecting on the
>>>>> exteranl bus?
>>>> Using a Synchronous FIFO implies that the read clock and the write
>>>> clock are in the same clock domain. Is your MCU supplying the FIFO's
>>>> clock or is the FPGA supplying the MCU's clock? If the clock sources
>>>> are different, then you either need an Asynchronous FIFO, or you need
>>>> to run the MCU and FPGA from the same clock.
>>>> HTH
>>>> -Dave Pollum
>>> It is in different clock, i tried altera's asynchronous FIFO which
>>> need two extra clock for reading.
>>> is there any better solution?

>> If your MCU is running much slower than the FPGA, you can use the
>> FPGA's internal clock to run the synchronous FIFO, and a little
>> state logic to generate the necessary (single cycle) pulses for
>> read and write from the MCU interface signals.

> unfortunately, the problem i met is on the contrary. MCU is much
> faster then FPGA, about 4 times.

- Just for info purposes what is the fpga clk rate and MCU rate?
- What is the fastest clk available on pwb?
- Does the MCU provide a clk at all for this interface? ie synchronous

Personally, I like to have an FPGA clk that is faster than any of my
interfaces, or I use a clk from the fastest source on the pwb, and make
my logic synchronous to that source, or I hope that if I have a high
speed interface, there is an external clk that I can use, and limit the
use of this clk within the fpga to just that interface..

That being said you are where you are.

You might want to look at using the clk multiplier function in the
Cyclone. You will be able to generate a higher clk fpga rate than
you currently have, treat the read pulse asynchronously, and use the
trailing edge detect I previously described. Since it is now
asynchronous you will have to make the single FF, two FF and decode
your edge detect off of these signals.


John Retta
Owner and Designer
Retta Technical Consulting Inc.

Colorado Based Xilinx Consultant

phone : 303.926.0068
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