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Old 11-09-2007, 03:39 PM
John Retta
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Default Re: FIFO interface design


>
> If your MCU is running much slower than the FPGA, you can use the
> FPGA's internal clock to run the synchronous FIFO, and a little
> state logic to generate the necessary (single cycle) pulses for
> read and write from the MCU interface signals.


In this case, logic is simply an edge detect.

ie.

reg read_level_q;
wire fifo_read_trailing_edge_det = ~read_level & read_level_q;

always @ (posedge clk)
begin
read_level_q <= read_level;
end


--

Regards,
John Retta
Owner and Designer
Retta Technical Consulting Inc.

Colorado Based Xilinx Consultant

email : [email protected]
web : www.rtc-inc.com
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