View Single Post
  #3 (permalink)  
Old 11-09-2007, 02:25 AM
Readon
Guest
 
Posts: n/a
Default Re: FIFO interface design

On Nov 9, 8:07 am, Dave Pollum <[email protected]> wrote:
> On Nov 8, 8:15 am, Readon <[email protected]> wrote:
>
> > i want to read & write data to/from a fifo placed in fpga. MCU's
> > external bus is connected to the chip. I am using the sync-fifo ip of
> > Altera CycloneII. The data bus and control signal are connected to
> > fifo directly. it's unfortune that when i read once from bus, data
> > would be read twice from fifo because there are two clock rising edges
> > during read signal(low active) is resetted. I think it will read more
> > datas from fifo if the read signal is resetted long enough.
> > Is there any good design for fifo interface connecting on the
> > exteranl bus?

>
> Using a Synchronous FIFO implies that the read clock and the write
> clock are in the same clock domain. Is your MCU supplying the FIFO's
> clock or is the FPGA supplying the MCU's clock? If the clock sources
> are different, then you either need an Asynchronous FIFO, or you need
> to run the MCU and FPGA from the same clock.
> HTH
> -Dave Pollum


It is in different clock, i tried altera's asynchronous FIFO which
need two extra clock for reading.
is there any better solution?

Reply With Quote