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Old 10-31-2007, 03:35 PM
Mike Lewis
Posts: n/a
Default Re: Is it possible to check how cache memories are mapped to FPGA block rams?


I have worked with an ARM926 soft core. This deliverable provided an
implementation guide as well as a simulation environment to verify the RAM
integration. I would have thought the ARM11 would have a similar thing.

Whether it is FPGA or ASIC the RAM integration follows the same process. The
RTL simulation environment will ensure you have correctly connected the


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