View Single Post
  #5 (permalink)  
Old 10-30-2007, 02:18 PM
Posts: n/a
Default Re: Is it possible to check how cache memories are mapped to FPGA block rams?

On Oct 30, 6:16 am, Wei Wang wrote:
> On Oct 29, 7:42 pm, Eric Smith wrote:
> > Perhaps if you post the actual project (or put a copy on a web site and
> > post a URL), some of us can take a look at it and try to help debug
> > it. Otherwise we don't have very much to go on.

> > Eric


> BTW, I suppose most of us in this group do not work for ourselves, only lazy
> university students would post their entire project and let somebody
> else do the work for them. Thanks!

Now, now. Don't be too hasty. That's what we do with Xilinx all the
time when their software tools don't work "just right" or you hit that
invisible brick wall that only someone with eyes from inside the brick
wall can tell you why the wall exists (read: Webcases).

So long as what you're working on is not proprietary, the nature of
"open source" mindedness is to share with others and gather feedback.
That's what posting your MHS file would provide.

Reply With Quote