On Feb 12, 5:09 pm, Jim Granville <[email protected]>
wrote:

> If you have an older design iteration archived, you could download that
> to check all the hardware is OK ?

Not for that device -- the design got too big. The smaller one was
done with 8.2.03, and I've downloaded that now -- I'll try it
tomorrow.

> You have checked the fitter pin-report to make sure it is not
> moving pins about ?

Yes I have. In some ways it's stranger than that -- take two pins
that should be a CPU databus (but are actually permanently low) -- if
I ground (internally) either one, the other works, however if I pull
either to VCC the other stays grounded.

> There have been other postings here about Xilinx CPLD flows,
> which suggest their PLD regression testing is, shall we say, "Casual".

As a user of about 10 different versions from DOS Viewlogic forward
I've never noticed that before. I've always found the software to be
rock solid, well tested and clearly documented ;-)