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Old 08-09-2006, 03:16 PM
Johannes Hausensteiner
Posts: n/a
Default Re: Newbie question

Hi André,

Thanks for your answer; yes I added my testbench to the ispLEVER
project and assosiated it to the FPGA chip. I get three entries in
right pane of the ispLEVER ProjectNavigator:
- VHDL Functional Simulation
- VHDL Post-Route Functional Simulation
- VHDL Post-Route Timing Simulation
When I double-click on any of them Modelsim is started and it compiles
and tries to load the design. In all three of them there are following
error messages in Modelsim:
-- snip ---
# ** Error: (vsim-3170) Could not find 'work.StimModule_Unknown'.
# Error loading design
# Error: Error loading design
# Pausing macro execution
-- snip ---
The name "work.StimModule_Unknown" is used for each and every design
I tried up to now.
When I replace this in the (by ispLEVER generated) do-files
(test_bench.fdo, test_bench.xdo, test_bench.tdo) with the name of the
testbench then the "Functional Simulation" will work.
The "Post-Route Functional Simulation" and the "Post-Route Timing
Simulation" will still refuse to load in Modelsim with the following
-- snip ---
# Loading work.tb_counter(test_counter)
# ** Error: (vsim-13) Recompile work.counter(everything) because
work.counter has changed.
# Error loading design
# Error: Error loading design
-- snip ---
This does not change when I actually recompile "counter",
"work.counter", or the whole design.

While once more double-checking I found out the following:
for the "Post-Route ... Simulation" ispLEVER decompiles what it has
routed to a VHDL file named "design.vho". This uses the architecture
name "Structure". For the testbench to be loaded correctly within
Modelsim is has (of course) to be of architecture "Structure", too
(which was in the case in my design). - OK, this one is clear; I can
live with the "work.StimModule_Unknown" thing.

So thank you for your replies!


[email protected] wrote:
> Hi Johannes,
> did you import the testbench file and associate it to the device in
> ispLEVER?
> By doing that you can start functional and timing simulation when
> marking
> the device.
> Besides are you using VHDL packages ?
> Rgds
> André
>> There is a "Post Place and Route Simulation" action available within
>> ispLEVER (actually it starts Modelsim), but this does not work.
>> Modelsim always complains "Error loading design".
>> What possibilities do I have to debug my design?
>> Thanks a lot,
>> Johannes


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