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Old 08-08-2006, 03:21 PM
Mike Treseler
Posts: n/a
Default Re: Newbie question

Johannes Hausensteiner wrote:

> I am doing my first FPGA/VHDL design.
> I coded the VHDL source files and simulated it successfully with
> Modelsim. Then I made the I/O pin assignments and made the .bit
> file and loaded it to the FPGA. To my disappointment only some of
> the signals are correct; the functionality of the system does not
> work.
> I am using ispLEVER and a Lattice LFEC33 FPGA.
> There is a "Post Place and Route Simulation" action available within
> ispLEVER (actually it starts Modelsim), but this does not work.
> Modelsim always complains "Error loading design".

Use modelsim directly from the command line or GUI.

> What possibilities do I have to debug my design?

Common first-time synthesis problems include:
Use of wait statements.
No clock.
No reset.
Inputs not synchronized.
Clock or reset on non-global pin.
Not using standard clocked process template.

If all else fails,
post your code to comp.lang.vhdl
Good luck.

-- Mike Treseler
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