Martin,

> Have you had a look in FPGA editor to see what's going on?

This is where I myself look dim: I did open up the NCD file in the FPGA
Editor. I didn't really know what to do to tell if the right
registering was occurring. All I could see was that all 4 DSP48s were
instantiated together in a little row. I've never used FPGA editor
before. I'm more familiar with PlanAhead for looking at that sort of
thing, but I don't have that on my laptop, my current working platform.

> Is it actually this bit of code that limits the timing?

Well, all I can say is that I don't think so. It could very well be
though, but I've tried writing the VHDL in very different ways, guided
by things I've found in one or two guides to instantiating the DSP48s
in VHDL. Every way I write the VHDL, the same performance is obtained.
The thing is that I can see that the synthesis tool is making some kind
of effort to pipeline the thing.

This is the critical path that comes out of the synthesis report if
this means anything to anyone:

Data Path: mult_inst/Mmult__n00001 to mult_inst/Mmult__n0000_35
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
DSP48:CLK->PCOUT47 1 4.399 0.000 mult_inst/Mmult__n00001
(mult_inst/Mmult__n00002_PCIN_to_mult_inst/Mmult__n00001_PCOUT_47)
DSP48:PCIN47->PCOUT47 1 2.363 0.000
mult_inst/Mmult__n00002
(mult_inst/Mmult__n00003_PCIN_to_mult_inst/Mmult__n00002_PCOUT_47)
DSP48:PCIN47->PCOUT47 1 2.363 0.000
mult_inst/Mmult__n00003
(mult_inst/Mmult__n00004_PCIN_to_mult_inst/Mmult__n00003_PCOUT_47)
DSP48:PCIN47->P35 1 2.270 0.534 mult_inst/Mmult__n00004
(mult_inst/Mmult__n0000_s_69)
FD 0.391 mult_inst/Mmult__n0000_0
----------------------------------------
Total 12.320ns (11.786ns logic, 0.534ns route)
(95.7% logic, 4.3% route)

Cheers,

Robin