On 25 May 2006 14:05:39 -0700, [email protected] wrote:

>Hello PPL,
>
>I would like to know what are the current implementations for the
>internal blocks inside a DSP48E. This of course applies to the new
>Virtex-5 FPGA. How is Xilinx building, at RTL, the 25 X 18 multiplier
>(is it a booth?) as well as the 48 X 48 adder blocks?

First of all there is no RTL (one which gets synthesized anyway).
Second I remember Xilinx licensing some IP from a high speed module
generator company a while back. Their design methodology was a little
more public.